Algorithm Engineering: 5th International Workshop, WAE 2001 by Gonzalo Navarro, Mathieu Raffinot (auth.), Gerth Stølting

By Gonzalo Navarro, Mathieu Raffinot (auth.), Gerth Stølting Brodal, Daniele Frigioni, Alberto Marchetti-Spaccamela (eds.)

This e-book constitutes the refereed lawsuits of the fifth Workshop on set of rules Engineering, WAE 2001, held in Aarhus, Denmark, in August 2001. The 15 revised complete papers provided have been conscientiously reviewed and chosen from 25 submissions. one of the themes addressed are implementation, experimental trying out, and fine-tuning of discrete algorithms; novel use of discrete algorithms in different disciplines; empirical study on algorithms and information constructions; and methodological matters in regards to the means of changing person requisites into effective algorithmic options and implemenations.

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Frigo and S. G. Johnson: The fastest Fourier transform in the west. MIT-LCSTR-728 Massachusetts Institute of technology, Sep. 11 1997. 27 Fractal Matrix Multiplication: Portability of Cache Performance 37 22. M. Frigo, C. E. Leiserson, H. Prokop and S. Ramachandran: Cache-oblivious algorithms. Proc. 40th Annual Symposium on Foundations of Computer Science, (1999). 27 23. E. D. Granston, W. Jalby and O. Teman: To copy or not to copy: a compiletime technique for assessing when data copying should be used to eliminate cache conflicts.

Prokop and S. Ramachandran: Cache-oblivious algorithms. Proc. 40th Annual Symposium on Foundations of Computer Science, (1999). 27 23. E. D. Granston, W. Jalby and O. Teman: To copy or not to copy: a compiletime technique for assessing when data copying should be used to eliminate cache conflicts. 410-419. 27 24. G. H. Golub and C. F. van Loan: Matrix computations. Johns Hopkins editor 3-rd edition. 28 25. F. G. Gustavson: Recursion leads to automatic variable blocking for dense linear algebra algorithms.

1 Introduction The ratio between main memory access time and processor clock cycle has been continuously increasing, up to values of a few hundreds nowadays. The increase in Instruction Level Parallelism (ILP) has been a significant feature: current CPUs can issue four/six instructions per cycle and the cost of a memory access is an increasingly high toll on overall performance of super-scalar/VLIW processors. The architectural response has been an increase in the size and number of caches, with a second level being available on most machines, and a third level becoming now popular.

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